The present invention relates to a method of manufacturing contact structures for integrated circuits and more particularly, manufacturing contact structures in submicron design rule integrated circuits by means of gold plating so as to prevent void formation due to self-shadowing during material deposition.
FIG. 2 is a cross-sectional view of a portion of an integrated circuit made by means of prior art processing technology which illustrates the problems inherent in producing a high aspect ratio contact structure.
FIG. 2, shows a silicon substrate 101, wherein semiconductor regions (not illustrated) such as diffusion layers are formed in its surface. In order to provide electrical isolation between these semiconductor regions and electrode wiring regions formed on the surface of silicon substrate 101, an insulation film comprising a silicon oxide film 102 5,000 .ANG. to 6,000 .ANG. thick is formed on the surface of silicon substrate 101 by a CVD method.
Contact holes 103 are formed in silicon oxide film 102 so as to provide physical pathways through it. At the bottoms of contact holes 103 silicon substrate contact regions 101a are exposed. Foundation metal layers 104 are formed on the surfaces of these opened contact regions 101a and on the inner surface sidewalls of contact holes 103, and on the surface of silicon oxide film 102 in portions peripheral to contact holes 103. These foundation metal layers 104 are constructed of 150 .ANG. thick Ti layer 104a, 1,000 .ANG. thick TiN layer 104b, 150 .ANG. thick Ti layer 104c, and 1,000 .ANG. thick Pt layer 104d, which are successively deposited over their surfaces by a sputtering method. Further, a wiring layer comprising Au layer 105 is adhered on the surface of Pt layer 104d of foundation metal layers 104 by non-electrolytic plating treatment, such that the interior portion of contact holes 103 are filled by Au layer 105.
Since the thickness of silicon oxide film 102 described above is 5,000 .ANG. to 6,000 .ANG., contact hole 103 is relatively narrow compared to its depth (i.e. the aspect ratio is high). Further, Ti layer 104a, TiN layer 104b, Ti layer 104c and Pt layer 104d are accumulated as foundation metal layers 104 on the inner surfaces of contact hole 103, making the width of the opening still narrower.
When the interior of contact holes 103 are filled by Au film 105 by a non-electrolytic plating treatment, there is insufficient circulation of new plating liquid toward bottom surface sides 103a of contact holes 103, so that the growth rate of Au layer 105 at the bottom surface sides 103a is less than at the sidewalls 103b. Accordingly, Au film 105 grows in such a manner that it pushes out from the sidewalls of contact holes 103, and as this is happening, the circulation of new plating liquid decreases at the bottom surface 103a, thus decreasing the growth rate of Au film 105 still further at bottom surface 103a. As the plating process continues, Au film 105 closes the contact openings while leaving voids 105a in the interiors of contact holes 103, as shown in FIG. 2.
When Au film 105 is formed in this manner, the contact resistance increases because of the decrease in the degree of coverage of foundation metal layers 104 by Au film 105. Further, over the long term cracks develop from voids 105a which result in a decrease in integrated circuit reliability.
Therefore a need exists for a contact manufacturing process which produces void-free contact structures having low contact resistance and high long term reliability. What is desirable is a method for achieving a low aspect ratio during the contact-plug plating process step, while maintaining the fine line geometries necessary in submicron processing.